1. Field of the Invention
This invention relates to the field of cache memories. More particularly, this invention relates to cache memories supporting variable cache line sizes.
2. Description of the Prior Art
In a cache memory, the size of the cache lines has a substantial influence on processor performance, and on the power consumption of the processor, the cache and the memory system. A cache line size which is too small will result in multiple small burst transactions being submitted to the memory system rather than a single large burst transaction, resulting in additional power consumption through inefficient use of SDRAM memory and an increase in CPU stall cycles due to more non-sequential accesses. In contrast, a cache line size which is too large will result in power being wasted due to non-required data being pre-fetched from memory, and will reduce the number of cache lines in the cache memory for a given cache size, thereby increasing the occurrence of conflict misses. It will therefore be appreciated that an improvement in processor performance and a reduction in power consumption can be sought by selecting an optimal cache line size. An optimal cache line size will minimise the number of burst transactions, only fetch data that is required, and minimise conflict misses. It will be understood that the term optimal cache line size in this context refers to a cache line size which is considered to provide a good compromise between the various requirements rather than any absolute standard.
However, studies have shown (“Adapting Cache Line Size to Application Behaviour”, Alexander Veidenbaum et al.) that no single optimal cache line size caters for all applications. An optimal cache line size depends upon the content (instructions or data), the task, and the memory segment. The optimal cache line size can change over time.
Two main cache line size optimisation schemes are currently known, these being static optimisation and dynamic optimisation. Static optimisation examines the program code and/or data to be supported and selects the most appropriate cache line size, which will be a compromise for all the code executed. Static optimisation cannot be effectively used where the software to be executed is not known in advance.
Dynamic optimisation schemes adjust the cache line size at run time. A number of dynamic schemes are possible. For instance, in one scheme, the cache is divided into a number of small physical cache lines. These cache lines can be grouped together to generate a larger virtual cache line. The current virtual line lengths are stored in a lower level of the memory hierarchy and are used to select the length of a line fill on a cache miss. When a line is in the cache, usage information, including current virtual line size, adjacent bit and usage counter, is kept with each line. During the time when a line is resident in the cache, the presence of an adjacent line is monitored by hardware. When a line is evicted from the cache, this information is used to recalculate the optimum line size, and this is stored back to a lower level of the memory hierarchy.
In an alternative scheme, a large cache line is provided, but only part of the cache line is used depending on the result of a prediction. In particular, a predictor is used to predict the line length which will be required for a line fill. This scheme reduces the efficiency of the cache by reducing the number of available lines. Another scheme uses a compiler to specify how much data to fetch on a cache miss. This requires either an additional instruction or for the instructions to be extended. This scheme reduces code density, and isn't updated automatically. In general, the dynamic schemes are power hungry because predictors have to be used on each cache eviction, and consume a large amount of hardware. These schemes may also cause additional latency to cache accesses, and may lose predictor information as a result of task switches.